Difference between revisions of "Xen 4.2 Limits"

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{{TODO|Should this be 256 for HVM? }}
 
{{TODO|Should this be 256 for HVM? }}
  
Note that in theory Xen supports 8192 VCPUs with PV, but event channel limitations (4k per guest) make it impossible for a guest this huge to
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Note that in theory Xen supports 8192 VCPUs with PV, but event channel limitations (4k per guest) make it impossible for a guest this huge to boot, as each vCPU is expected to minimally require 2 of them (timer vIRQ and IPIs). The guest limits stated above are limits that have been tested. However, it is possibly to exceed these in theory.
boot, as each vCPU is expected to minimally require 2 of them (timer vIRQ and IPIs). The limits stated above, are limits that have been tested. However, it is possibly to exceed these in theory.
 
  
 
== Other Limits ==
 
== Other Limits ==

Revision as of 08:19, 14 August 2012

Icon todo.png To Do:

This is a work in progress. Feel free to add requests for more to the talk page or add additional information here


This document contains information about limits of Xen 4.2.

CPUs & Memory

  • Xen can scale up to 4,095 host CPUs with 5Tb of RAM.
  • Using Para Virtualization (PV), Xen supports a maximum of 512 VCPUs with 512Gb RAM per guest.
  • Using Hardware Virtualization (HVM), Xen supports a maximum of 128 VCPUs with 512Gb RAM per guest.
Icon todo.png To Do:

Should this be 256 for HVM?


Note that in theory Xen supports 8192 VCPUs with PV, but event channel limitations (4k per guest) make it impossible for a guest this huge to boot, as each vCPU is expected to minimally require 2 of them (timer vIRQ and IPIs). The guest limits stated above are limits that have been tested. However, it is possibly to exceed these in theory.

Other Limits

  • Maximum of 32K interrupts and 2k PCI segments: this limits the number of devices that can be used in two ways:
    • The number of devices many can be attached to the system must fit into 2k PCI segments, i.e. 2k * 256 [buses] * 32 [devices] * 8 [functions])
    • The number of hardware interrupts they may surface (one would expect at least one interrupt per device function, so this is the stricter of the two limitations).