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  • /files/xensummitboston08/Cache-Virtualization.pdf
    101 KB (13,936 words) - 11:40, 21 June 2013
  • === Increase cache hits for dom0 vCPUs in the no pinning case === ...s closer to what happens when xpinning its vcpus. This should increase the cache hits and potentially increase the performance of dom0.
    18 KB (2,883 words) - 12:41, 10 July 2013
  • ...d - as we bypass the DIMMs and instead the CPU can process the data in the cache. ...data longer in the cache and the guest can process the data right off the cache.
    35 KB (5,643 words) - 18:07, 2 February 2017
  • ...and Jun will chase up VMX maintainers inside Intel re: GPU Passthrough and cache attributes to "comment on certain aspects of EPT and why IOMMU related thin
    3 KB (434 words) - 16:11, 16 April 2014
  • ...U queue support; this new component aims to reduce the lock contention and cache effects provoked by the presence of a single per-device queue of I/O reques
    9 KB (1,442 words) - 18:06, 2 February 2017
  • * Cache QoS Monitoring - hypercalls ( Chao Peng, Dongxiao Xu, and Shantong Kang)
    7 KB (957 words) - 13:38, 27 February 2015
  • ...ul 2014)]. This is automatically used if you use mirror, snapshot, thin or cache dm targets.
    2 KB (315 words) - 00:13, 11 January 2015
  • * Haswell Cache QoS Monitoring aka Intel Resource Director Technology is “a new area of a
    12 KB (1,829 words) - 16:09, 5 March 2015
  • ! Cache Monitoring Technology (CMT) ! style="font-weight:normal"| CMT can be used to monitor Last Level Cache (LLC) usage by application threads. With this information, administrators a
    11 KB (1,522 words) - 15:01, 14 May 2018
  • Checkout on commit, hash: f7ca1f7, net: sh-eth: Add cache writeback control after setting bit of DMA descriptor
    5 KB (660 words) - 12:37, 20 October 2015
  • ...d - as we bypass the DIMMs and instead the CPU can process the data in the cache. ...data longer in the cache and the guest can process the data right off the cache.
    34 KB (5,345 words) - 18:06, 2 February 2017
  • Similarly, the CACHE interface is a caching object allocator – similar in some ways to the sla
    27 KB (4,608 words) - 15:25, 10 February 2015
  • * Intel Cache Allocation Technology
    5 KB (681 words) - 09:05, 10 August 2015
  • ...che Allocation Technology]] allows system administrators to assign more L3 cache capacity to individual VMs, resulting in lower latency and higher performan
    8 KB (1,220 words) - 14:37, 9 October 2015
  • ...ning of cache capacity to the characteristics of the workload. CDP extends Cache Allocation Technology (CAT) by providing separate code and data masks per C ...n.org/docs/unstable/man/xl.1.html#CACHE-ALLOCATION-TECHNOLOGY xl man page (CACHE-ALLOCATION-TECHNOLOGY)]
    16 KB (2,394 words) - 07:36, 24 April 2017
  • ...The introduction of CDP allows isolation of code/data within the shared L3 cache of multi-tenant environments, reducing contention and improving performance ...mmit;h=d532f45d94c412d6ee0491cd0b44946373ff2268 d532f45]: libxl: don't add cache mode for qdisk cdrom drives [Jim Fehlig]
    294 KB (54,365 words) - 10:43, 17 June 2016
  • ...e5aa185cd865b95b49e7b303 9bb1865]: x86/vm_event: allow overwriting Xen's i-cache used for emulation [Tamas K Lengyel] ...1387d5c6dd336f6fea8404c1ba8a89cbd ed6869d]: xen/arm: arm64: Add Cortex-A53 cache errata workaround [Julien Grall]
    176 KB (32,513 words) - 10:56, 6 December 2016
  • ...and performance are already monitored such as CPU and memory utilization, cache misses etc. by utilizing an existing API. In Uniserver we plan to enhance s ...th memory errors (1/double bit flip) and CPU errors (CPU voltage/frequency/cache interrupt). In my previous work (2016.10-2017.2) I simulate error injection
    20 KB (3,233 words) - 10:30, 27 February 2017
  • cache size: 8192 KB
    22 KB (3,566 words) - 13:43, 18 April 2017
  • total used free shared buff/cache available r b swpd free buff cache si so bi bo in cs us sy id wa st
    65 KB (10,023 words) - 13:25, 27 September 2017

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