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  • * TMEM allows improved utilization of unused (for example page cache) PV guest memory. more information: http://oss.oracle.com/projects/tmem/
    21 KB (3,184 words) - 14:37, 11 September 2012
  • ...switches to happen too frequently, which may lead to trashing of CPU and cache(s). The best timeslice value, though, is highly workload dependant. Credit ...s, but at the cost of increased the overhead from context, and reduced CPU cache effectiveness.
    9 KB (1,463 words) - 05:33, 28 June 2018
  • ...system won't hit a machine check when an OS bug leads access with a wrong cache type. A Machine check is hard to analyze and can be seen as a hardware bug
    40 KB (6,191 words) - 11:42, 13 January 2016
  • ...In general, this is a good rule, since each VM then has a large cache, and cache-misses are minimised. However, as explained above, this rule is not great f
    43 KB (7,032 words) - 14:21, 30 April 2014
  • ...e will never need to change them. Plus it is very convenient to be able to cache them-- I'm keen to exploit this to make the event mechanism more efficient.
    4 KB (622 words) - 12:43, 11 July 2013
  • Populate the in-memory cache from the connection containing the most recent generation of database (see '''(slave) Update in-memory cache'''
    10 KB (1,608 words) - 21:24, 20 January 2015
  • ...an with it disabled. This may be due to many factors, including increased cache footprint, or quirks in the microarchitectural implementation of the partic
    4 KB (660 words) - 11:25, 13 October 2016
  • ...d - as we bypass the DIMMs and instead the CPU can process the data in the cache. ...data longer in the cache and the guest can process the data right off the cache.
    23 KB (3,671 words) - 19:04, 18 February 2016
  • ...enables DMA remapping, which can be configured for each device. There is a cache called IOTLB which improves performance.
    73 KB (11,255 words) - 13:01, 25 November 2016
  • | "Segment Clean" & "Cache" feather of HLFS which is sub-project of Cloudxy ...eatures, which are "clean segment under tree snapshots" feature and "block cache and write-back" feather during GSOC 2012.<br>
    6 KB (951 words) - 18:07, 2 February 2017
  • ...d by the policy, just like SELinux (avc being an acronym for Access Vector Cache). These log events can be viewed with xl dmesg:
    35 KB (5,495 words) - 09:02, 27 May 2015
  • ...rk device with external connectivity (or connectivity to your local mirror/cache) is required for the duration of the installation process.
    15 KB (2,420 words) - 19:00, 9 February 2022
  • ...ity settings to assist this). Due to potential information leakage through cache timing attacks between domains sharing the same hyperthreaded CPU core, we ...fashion via shared buffer cache mappings to the same file. A shared buffer cache could also avoid some IO, and yield memory savings. Implementing this for P
    80 KB (13,457 words) - 15:58, 25 November 2016
  • ...er via ''make install'' or a packageballl) you rebuild your dynamic linker cache by running:
    20 KB (3,075 words) - 20:46, 9 March 2022
  • [ 6.588454] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes) [ 6.599902] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes)
    73 KB (8,839 words) - 03:30, 26 March 2015
  • ...nformation about cryptographic keys can be pieced together just by knowing cache patterns or the amount of time spent on certain operations; having VMs from
    4 KB (741 words) - 08:35, 21 February 2014
  • ** Enable cleancache driver to cache clean pages if tmem is present
    51 KB (8,262 words) - 07:44, 28 May 2013
  • cache flush and loading descriptor table base addresses (see [[#http://wiki.xen.o
    27 KB (4,330 words) - 09:13, 27 May 2015
  • ...CPUs". For instance, one run-queue for all the pCPUs that have a common L3 cache, as credit2, another scheduler present in Xen, is doing already. Completing
    45 KB (7,151 words) - 18:07, 2 February 2017
  • |Desc=Setting HCR.FB will upgrade local flush instructions (TLB, instruction cache, branch predictor) to innershareable. It would be nice to benchmark the pe
    2 KB (257 words) - 10:22, 27 April 2016
  • /files/xensummitboston08/Cache-Virtualization.pdf
    101 KB (13,936 words) - 11:40, 21 June 2013
  • === Increase cache hits for dom0 vCPUs in the no pinning case === ...s closer to what happens when xpinning its vcpus. This should increase the cache hits and potentially increase the performance of dom0.
    18 KB (2,883 words) - 12:41, 10 July 2013
  • ...d - as we bypass the DIMMs and instead the CPU can process the data in the cache. ...data longer in the cache and the guest can process the data right off the cache.
    35 KB (5,643 words) - 18:07, 2 February 2017
  • ...and Jun will chase up VMX maintainers inside Intel re: GPU Passthrough and cache attributes to "comment on certain aspects of EPT and why IOMMU related thin
    3 KB (434 words) - 16:11, 16 April 2014
  • ...U queue support; this new component aims to reduce the lock contention and cache effects provoked by the presence of a single per-device queue of I/O reques
    9 KB (1,442 words) - 18:06, 2 February 2017
  • * Cache QoS Monitoring - hypercalls ( Chao Peng, Dongxiao Xu, and Shantong Kang)
    7 KB (957 words) - 13:38, 27 February 2015
  • ...ul 2014)]. This is automatically used if you use mirror, snapshot, thin or cache dm targets.
    2 KB (315 words) - 00:13, 11 January 2015
  • * Haswell Cache QoS Monitoring aka Intel Resource Director Technology is “a new area of a
    12 KB (1,829 words) - 16:09, 5 March 2015
  • ! Cache Monitoring Technology (CMT) ! style="font-weight:normal"| CMT can be used to monitor Last Level Cache (LLC) usage by application threads. With this information, administrators a
    11 KB (1,522 words) - 15:01, 14 May 2018
  • Checkout on commit, hash: f7ca1f7, net: sh-eth: Add cache writeback control after setting bit of DMA descriptor
    5 KB (660 words) - 12:37, 20 October 2015
  • ...d - as we bypass the DIMMs and instead the CPU can process the data in the cache. ...data longer in the cache and the guest can process the data right off the cache.
    34 KB (5,345 words) - 18:06, 2 February 2017
  • Similarly, the CACHE interface is a caching object allocator – similar in some ways to the sla
    27 KB (4,608 words) - 15:25, 10 February 2015
  • * Intel Cache Allocation Technology
    5 KB (681 words) - 09:05, 10 August 2015
  • ...che Allocation Technology]] allows system administrators to assign more L3 cache capacity to individual VMs, resulting in lower latency and higher performan
    8 KB (1,220 words) - 14:37, 9 October 2015
  • ...ning of cache capacity to the characteristics of the workload. CDP extends Cache Allocation Technology (CAT) by providing separate code and data masks per C ...n.org/docs/unstable/man/xl.1.html#CACHE-ALLOCATION-TECHNOLOGY xl man page (CACHE-ALLOCATION-TECHNOLOGY)]
    16 KB (2,394 words) - 07:36, 24 April 2017
  • ...The introduction of CDP allows isolation of code/data within the shared L3 cache of multi-tenant environments, reducing contention and improving performance ...mmit;h=d532f45d94c412d6ee0491cd0b44946373ff2268 d532f45]: libxl: don't add cache mode for qdisk cdrom drives [Jim Fehlig]
    294 KB (54,365 words) - 10:43, 17 June 2016
  • ...e5aa185cd865b95b49e7b303 9bb1865]: x86/vm_event: allow overwriting Xen's i-cache used for emulation [Tamas K Lengyel] ...1387d5c6dd336f6fea8404c1ba8a89cbd ed6869d]: xen/arm: arm64: Add Cortex-A53 cache errata workaround [Julien Grall]
    176 KB (32,513 words) - 10:56, 6 December 2016
  • ...and performance are already monitored such as CPU and memory utilization, cache misses etc. by utilizing an existing API. In Uniserver we plan to enhance s ...th memory errors (1/double bit flip) and CPU errors (CPU voltage/frequency/cache interrupt). In my previous work (2016.10-2017.2) I simulate error injection
    20 KB (3,233 words) - 10:30, 27 February 2017
  • cache size: 8192 KB
    22 KB (3,566 words) - 13:43, 18 April 2017
  • total used free shared buff/cache available r b swpd free buff cache si so bi bo in cs us sy id wa st
    65 KB (10,023 words) - 13:25, 27 September 2017
  • [75292.358817] sd 4:0:0:0: [sdb] Assuming drive cache: write through [75292.361992] sd 4:0:0:0: [sdb] Assuming drive cache: write through
    79 KB (11,532 words) - 06:20, 6 June 2017
  • SSTATE_DIR -- set to a local directory for build cache files to speed up subsequent builds
    4 KB (580 words) - 20:39, 16 April 2024
  • ...h=8f57758311d816c66e88cfcfdc91f986f59345ad 8f57758311]: docs: Specify that cache-clean-interval is only supported in Linux [Alberto Garcia] ...mmit;h=91203f08f0ca66f1a6aba1d0e5ef62ed98fb3234 91203f08f0]: qcow2: Allow 'cache-clean-interval' in Linux only [Alberto Garcia]
    641 KB (116,056 words) - 09:51, 28 June 2017
  • ...e hardware Xen runs. This allows users to make better use of the shared L2 cache depending on the VM characteristic (e.g. priority).
    11 KB (1,776 words) - 14:37, 5 December 2017
  • === Mitigations against Cache Side-channel Attacks ===
    7 KB (1,044 words) - 11:56, 15 June 2018
  • ...han 700MB on idling guests. And this takes into account guests' <code>buff/cache</code> that is still allowed to live, which saves lots of disk I/O hence in
    2 KB (357 words) - 12:57, 13 February 2020
  • * SE3: Hardware isolation shall be supported (cache, interrupts, IOMMUs, firewalls, etc.).
    3 KB (414 words) - 01:17, 15 May 2019
  • ** Cache Coloring ** In Progress: Cache Coloring upstreaming
    2 KB (198 words) - 22:21, 11 August 2022
  • ** Scrubbing of guest memory which is signaling other cores to make sure cache is synced on all cores. ...em. As this might alter the guest timings and have other bad side effects (cache or TLB flushes required), a real time guest should have a configuration usi
    37 KB (5,662 words) - 15:13, 16 June 2022
  • = Cache Coloring and Deterministic Interrupt Latency = ...L2 cache in software using a technology called "Cache Coloring". Xen with Cache Coloring has a '''deterministic interrupt latency of 4 microseconds''' on X
    3 KB (403 words) - 00:00, 7 October 2022

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